Job Description

Role: Physical Design Architect
Location: San Jose CA (Onsite); Contract





Responsibilities:

• Work closely with logic design team to define physical architecture and drive physical aspects during the design cycle.
• Collaborate across teams (physical design logic design package DFT and test).
• Handson synthesis and PnR using industry standard tools for highspeed digital designs in advanced process nodes.
• Perform all aspects of signoff including power timing physical verification checks and design closure.

Must have experience

• Experience in Semiconductor domain
• 1520 years of experience in Physical Design and timing closure.
• Handson experience in synthesis PnR and STA using Cadence/Synopsys tools for complex digital designs in 7nm and below.
• Must have experience of multiple large SoC tapeouts in advanced nodes including handson experience in chiplevel physical design and STA closure.
• Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs expertise in timing closure at block/chip levels and ECO flows.

Logic Design,Physical Design,PNR,SoC,ASIC,CPU design,Semiconductor,Timing Closure

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